搜索资源列表
SRAM@DMA实验
- ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
SRAM_Controller
- SRAM Controller For Altera SOPC Builder and NIOS on DE2 kit board
sdrsdramuse
- 一篇讲解ALTERA的FPGA如何实现SDR SRAM的指导文章。很有指导意义。
altera_avalon_cy7c1380_ssram
- 关于altera的SRAM的读写控制IP代码，有兴趣的朋友可以下去
61WV102416ALL(ISSI_1M-x-16_SRAM)
- manuel of altera DE2 SRAM
altera_sdram
- Simple SDRAM controller source code for Altera DE2 board
sls_sram_16_bit
- altera NIOS软核系统中构建外接SRAM接口的例子-altera NIOS soft-core system to build external SRAM interface example
fpga_sram
- Altera cyclone ep1c6对sram idt71系列的读写时序控制-Altera cyclone ep1c6 of sram idt71 series of read and write timing control
niossramflash
- 在altera FPGA ep3c25器件上实现niosii+sram+flash-Altera FPGA ep3c25 in devices to achieve niosii+ sram+ flash
niossram
- altera fpga ep3c25器件微处理器开发，niosii+sram, 已编译通过，可直接下载到开发板-altera fpga ep3c25 the development of microprocessor devices, niosii+ sram, compiled through, can be directly downloaded to the development board
UART_DMA
- 基于ALTERA公司的NIOSII的串口通信DMA传输设计-NIOSII based on ALTERA s DMA transfer of the serial communication design
de2_lcm_ccd_sram
- 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
SRAM_Controller
- Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
bemicro_lab_ver
- be micron sram file downloaded from altera be-micro
vhdl_sram_ctrl
- Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus -Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus II
SRAM_Controller
- altera 大学计划 程序包的sram controller ip-altera University Program package sram controller ip
das3580sch
- das3580开发板原理图，■ Altera CycloneII EP2C8Q208C8N 的FPGA器件； ■ EPCS4 – 4Mbit 串行配置器件； ■ JTAG和AS双模式下载口； ■ 512Kbyte 10ns级SRAM器件构成双数据通道； ■ Cy7c68013a_128axc高性能USB2.0控制芯片；-das3580 development board schematics, ■ Altera CycloneII EP2C8Q208C8N the FPG
qdr2_sram
- qdr2 sram 在altera 平台上的实际使用-qdr2 sram platform in the actual use of altera
SRAM_1wait
- The aim of this vhdl file is to create a simple interface betwhen the sram and a basic processor on a semisync data bus. This was made using the test board DE2 from Altera.
添加库2
- 在modelsim中实现硬件库的调用，实现类似SRAM的仿真(Implement the call of the hardware Library in Modelsim and implement the simulation like SRAM)